1. Field of the Invention
The invention relates to a memory, a circuit for reading information stored in the memory, and a method of reading information stored in the memory.
2. Description of Related Art
A conventional memory circuit is now described. The conventional memory circuit comprises a data storage section made up of a plurality of word lines and a plurality of bit lines which are arranged in a grid shape, a pre-charge circuit for supplying an electric charge to each bit line, an address decoder for supplying the electric charge to a selected specific word line, a level detection circuit for detecting a voltage of each bit line, and a latch circuit for temporarily holding (latching) information as the voltage detected by the level detection circuit.
Although the word lines and the bit lines in the data storage section are arranged in a grid shape, these lines are not electrically directly connected to each other at the intersections of these lines in the grid shape arrangement. However, there is a case that transistors corresponding to the intersections are arranged at each intersection. Data is written in the data storage section depending on the presence or absence of the transistor. If there exist transistors arranged corresponding to the intersections, each transistor is electrically connected to a word line of the corresponding intersection at its gate, to a bit line thereof at its source, and to a ground at its drain.
Dummy bit lines are provided opposite to the address decoder via the data storage section. The dummy bit lines are arranged at the position more faraway from the address decoder than any other bit lines. The configuration and the connection relation of the dummy bit lines are substantially the same as those of other bit lines. However, for the dummy bit lines, there exist corresponding transistors at all the intersections between the dummy bit lines and the word lines.
The operations of the conventional memory and the memory read circuit are described next.
The pre-charge circuit supplies an electric charge to each bit line in response to a clock signal which is supplied from an external device. It is natural that a voltage of each bit line rises upon receipt of the electric charge from the pre-charge circuit.
The address decoder designates one specific word line upon receipt of a signal from an external device, and supplies the electric charge to the selected word line. Then, a voltage of that word line rises so that the transistor connected to the word line turns ON.
If a transistor corresponding to the intersection between some bit line and the designated word line exists at the intersection, the electric charge which is supplied to that bit line leaks to the ground through the transistor. Accordingly, the voltage of that bit line drops. On the contrary, if a transistor corresponding to the intersection between some bit line and the designated word line does not exist at the intersection, the voltage of that bit line is held high.
The level detection circuit detects the magnitude of the voltage of each bit line soon after the address decoder supplies the electric charge to the word lines, and outputs the magnitude of the voltage to the latch circuit as data. The latch circuit latches the data received from the level detection circuit and reads the latched data.
When reading data, a timing for detecting the magnitude of the voltage of the bit line presents a problem. The dummy bit lines are used for designating the timing for reading data.
When the address decoder designates a specific word line and supplies the electric charge to the designated word line, the voltage of the word line rises first in the order of those close to the address decoder due to a capacitance and a resistance of the word line per se. Meanwhile, as mentioned earlier, the dummy bit lines are arranged at the position more faraway from the address decoder than any other bit lines. Accordingly, after the gates of all the transistors corresponding to the intersections between the designated word line and the other bit lines turn ON, the gates of the transistors corresponding to the intersections between the designated word line and the dummy bit lines turn ON last. The detection of the magnitude of the voltage of the bit line utilizes this character.
That is, for the above reason, the dummy bit lines are slow in drop of the voltage compared with other bit lines. Accordingly, when the voltage of the dummy bit lines is lower than a certain level, the level detection circuit detects the voltage of the other bit lines. The reason is that the bit line, which is to drop in voltage of the other bit lines, sufficiently drop in voltage.
By use of the method of detecting the magnitude of the voltage of the bit lines, the magnitude of the voltage of the bit lines can be quickly detected, thereby reading data at high speed.
However, the conventional memory circuit has the following problems. That is, a parasitic capacitance is generated between the adjoining bit lines of the bit lines in the data storage section. Accordingly, even if a transistor corresponding to the intersections between the bit lines and the designated word line does not exist at each intersection, the voltage of the bit lines temporarily drops due to the generation of the parasitic capacitance. There occurs a case where the amount of drop of the voltage exceeds the threshold voltage of the level detection circuit depending on the magnitude of the parasitic capacitance. If such a case occurs, the voltage of the bit line, which has to be decided high, is decided to be low. As a result, there occurs malfunction such that the output from the latch circuit is rendered wrong.